The module "E1 Framer" was developed for Altera Cyclone family devices in Quartus 4.2 SP1.

It is intend for interface between ST-BUS protocol(4 wire interface including Clock, FS, DataTx and Data RX signals which described in datasheet for MITEL E1 Framer) and G.703, G704 2048 kbit/s. It works both master as slave mode. It also implements CRC4 error checking. It has the standard Intel interface with internal SRAM for reading and writing channel signalization.

National bits, Alarm bits and control bits such as master/slave mode and others are accessible for read and write operations through standard Intel interface.

It supports three types of E1 in-line coding. The first is HDB-3 (two signals per each data flow direction manage transistor-transformer scheme), the second is differential Manchester and the third is binary encoding with clock signal.

This module occupies about 28% of logic elements, approximately 2% of SRAM and one PLL in EP1CS3 chip.